1. Field of the Invention
The invention relates generally to the field of programmable logic arrays, and more specifically to self-timed programmable logic arrays having precharge circuitry for precharging minterm and output lines prior to decoding of the input signals and encoding of the output signals.
2. Description of the Prior Art
Since digital integrated circuits have been fabricated using large and very large scale integration ("LSI" and "VLSI") circuit techniques, programmable logic arrays have become popular mechanisms for implementing control logic circuits, such as state sequencers and state decoders, as well as a number of circuits previously implemented using combinational logic. A programmable logic array receives a plurality of input signals, and in response to the pattern of asserted and negated input signals, generates a plurality of output signals having a selected pattern of asserted and negated signals. The encoding of the input signals, that is, the particular input signals which are asserted and negated, determines the encoding of the output signals.
A programmable logic array is divided into two sections, or "planes", one functioning as a decoder and the other functioning as an encoder. The two sections are connected by a plurality of conductors, which are termed "minterm" conductors. The decoder section receives the input signals, and, based on their encoding, enables one or several of the minterm conductors. The enabled minterm conductors, in turn, cause the encoder to assert or negate the output signals in a selected pattern.
The circuits comprising the decoder plane operate to perform an AND function to enable each of the minterm conductors. Each AND circuit receives the true or complements of selected input signals. In response to a predetermined encoding, only particular minterm conductors are selected, that is, they have a different condition (high or low voltage level) than do the rest.
The circuits comprising the encoder plane effectively operate to perform an OR function, with each output line being driven by one circuit performing the OR function. The input signals to each OR circuit are the signals on the minterm conductors from the decoder section. When a minterm conductor is selected, the OR circuits connected to that minterm conductor establish the conditions of the output lines.
A primary benefit of using a programmable logic array is that the array typically can have a very regular physical shape on the integrated circuit chip. The input lines to the circuits performing the AND function, which include the true and/or complement of the input signals, and the output bit lines from the OR circuits in an physical implementation of a typical VLSI programmable logic array are all largely disposed in parallel. In addition, the minterm conductors are largely disposed orthogonally to the input and output lines. Each AND circuit is implemented using a plurality of transistors, with one transistor being used for each input signal, or its complement, which controls the minterm conductor. Each transistor is connected between the associated minterm conductor and ground and controlled by the signal on an input (or complement) line.
To speed operation of the programmable logic arrays, the minterm conductors and the output bit lines are commonly precharged, that is, they are placed in a selected electrical condition, typically a high voltage condition prior to enabling the AND and OR circuits to operate, which allows the signals to be generated more quickly. In the past, to prevent the input signals from affecting the precharge operation, gates have been placed on the input lines and the minterm conductors between the decoder and encoder sections to disable transmission of the input signals onto the input lines and transmission of the signals over the minterm conductors from the decoder section to the encoder section. However, the addition of the gates effectively disturbs the regular layout of the lines in the programmable logic array. In addition, the additional gates adds delays in the signal paths, which slows the operation of the programmable logic array.